View NX2141CMTR_1224395.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nx2141 1 rev. 1.6 05/15/07 off on comp 32k 10k 100uf 1uh +1.05v 10a vout nx2141 gnd ldrv hdrv sw fb bst pvcc 1uf 1uf 25tqc33m 25v,33uf vin1 +8 to 20v mbr0530t1 m1 m2 1uh co 2*2r5tpe220mc (220uf,12mohm) 0.1uf 1.5k 2.2nf 2.3k 15nf 1nf vin vin2 +5v 16 1 17 15 3 11 12 13 8 en 9 pgood 5 10k vcc 14 1uf 10 pgnd 2 typical application description the nx2141 controller ic is a compact synchronous buck controller ic designed for step down dc to dc con- verter applications with voltage feedforward functionality. voltage feedforward provides fast response, good line regulation and nearly constant power stage gain under wide voltage input range. the nx2141 controller is opti- mized to convert single supply up to 24v bus voltage to as low as 0.8v output voltage. internal uvlo keeps the regulator off until the supply voltage exceeds 7v where internal digital soft starts get initiated to ramp up output. the nx2141 employs fixed current limiting and fb uvlo followed by hiccup feature. other features includes: 5v gate drive capability , adaptive dead band control, avail- able in 16 lead mlpq and 10 lead msop package. n bus voltage operation from 7v to 24v n less than 1ua shutdown current with enable low n excellent dynamic response with input voltage feed- forward and voltage mode control n internal digital soft start function n fixed internal hiccup current limit n fb uvlo followed by hiccup feature n power good indicator available n start into precharged output n pb-free and rohs compliant ordering information features single channel mobile pwm controller with feedforward and enable applications n notebook pc n graphic card on board converters n on board dc to dc such as 12v to 3.3v, 2.5v or 1.8v n set top box and lcd display advance data sheet figure1 - typical application of nx2141(mlpq) device temperature package frequency pb-free NX2141CMTR -40 o c to 85 o c mlpq-16l 200khz yes nx2141cutr -40 o c to 85 o c msop-10l 200khz yes pb free product
nx2141 2 rev. 1.6 05/15/07 absolute maximum ratings vcc to gnd & bst to sw voltage ...................... -0.3v to 6.5v vin to gnd ........................................................ -0.3v to 30v bst to gnd voltage .......................................... -0.3v to 35v sw to gnd ....................................................... -2v to 35v all other pins ..................................................... -0.3v to 6.5v storage temperature range ................................ -65 o c to 150 o c operating junction temperature range ................ -40 o c to 125 o c esd susceptibility ............................................ 2kv caution: stresses above those listed in "absolute maximum ratings", may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. package information 16-lead plastic mlpq 10-lead plastic msop electrical specifications unless otherwise specified, these specifications apply over vcc =5v, vin=12v and t a = -40 o c to 85 o c . typical values refer to t a = 25 o c . 9 10 11 12 4 3 2 1 pgnd bst ldrv nc en nc fb comp 8 7 6 5 nc vin pgood nc 16 15 14 13 vcc hdrv sw pvcc agnd 17 parameter sym test condition min typ max units reference voltage ref voltage v ref 0.8 v ref voltage line regulation 0.2 % supply voltage(vcc) v cc voltage range v cc 4.75 5.25 v operating quiescent current i q en=high 1.5 5 ma shut down current i sd en=low 1 ua vcc uvlo v cc -threshold v cc _uvlo v cc rising 4.4 v v cc -hysteresis v cc _hyst v cc falling 0.2 v supply voltage(vin) v in voltage range v in 7 25 v input voltage current vin=24v 24 40 ua shut down current en=low 1 ua o ja cw q?46/ o ja cw q?200/ 4 3 2 1 7 8 9 10 bst ldrv gnd hdrv vcc fb comp sw 5 vin 6 en
nx2141 3 rev. 1.6 05/15/07 n parameter sym test condition min typ max units vin uvlo v in -threshold v in _uvlo v cc rising 6 v v in -hysteresis v in _hyst v cc falling 0.5 v oscillator (rt) frequency f s 200 khz frequency over vin -5 5 % ramp-amplitude voltage v ramp vin=20v 2 v ramp offset 0.8 v ramp/vin gain 0.1 v/v max duty cycle 88 % min on time 150 ns error amplifiers transconductance 2500 umho input bias current ib 100 na comp sd threshold 0.3 v vref and soft start soft start time tss f s =200khz 10 ms high side driver (cl=3300pf) rise time thdrv(rise) 10% to 90% 50 ns fall time thdrv(fall) 90% to 10% 50 ns low side driver (cl=3300pf) output impedance, sourcing current r source (ldrv) i=200ma 1 ohm output impedance, sinking current r sink (ldrv) i=200ma 0.5 ohm rise time tldrv(rise) 10% to 90% 50 ns fall time tldrv(fall) 90% to 10% 50 ns fixed ocp ocp voltage threshold 320 mv enable enable hi threshold 1.4 v enable low threshold 0.4 v ohm 0.8 30 ns 30 ns deadband time tdead(h to l) sw going low to ldrv going high, 10% to 10% tdead(l to h) deadband time ldrv going low to hdrv going high, 10% to 10% output impedance , sinking current r sink (hdrv) i=200ma 1 ohm output impedance , sourcing current r source (hdrv) i=200ma
nx2141 4 rev. 1.6 05/15/07 pin descriptions pin symbol pin description this pin supplies the internal 5v bias circuit. a 1uf ceramic capacitor is placed as close as possible to this pin and ground pin. this pin supplies voltage to high side fet driver. a high freq minimum 0.1uf ceramic capacitor is placed as close as possible to and connected to this pin and sw pin. power ground. this pin is the error amplifiers inverting input. this pin is connected via resistor divider to the output of the switching regulator to set the output dc voltage. this pin is the output of the error amplifier and together with fb pin is used to compensate the voltage control feedback loop. this pin is connected to source of high side fets and provide return path for the high side driver. high side gate driver output. low side gate driver output. pull up this pin to vcc for normal operation. pulling this pin down below 0.4v shuts down the controller and resets the soft start. bus voltage input provides power supply to oscillator and vin uvlo signal. an open drain output that requires a pull up resistor to vcc or a voltage lower than vcc. when fb pin reaches 90% of the reference voltage, pgood changes from lo to hi state. supply voltage for the low side fet drivers. a high frequency 1uf ceramic cap must be connected from this pin to the pgnd pin as close as possible. vcc bst gnd fb comp sw hdrv ldrv en vin pgood (mlpq only) pvcc parameter sym test condition min typ max units power good(mlpq only) threshold voltage as % of vref fb ramping up 90 % hysteresis 5 % fbuvlo feedback uvlo threshold percent of nominal 65 70 75 % over temperature threshold 150 c hysteresis 20 c
nx2141 5 rev. 1.6 05/15/07 block diagram agnd bias generator 1.25v 0.8v bst hdrv sw pvcc ldrv fb osc r s q digital start up uvlo por control logic ocp comparator vcc ramp 0.3v comp oc start start hiccup logic oc 1.3v clamp 0.6v clamp start pwm comp 320mv 0.8v en disable disable vin 6v/ 5.5v vin pgood fb 0.85vref /0.90vref por fb 70%*vp ss_half_done pgnd figure 2 - simplified block diagram of the nx2141(mlpq)
nx2141 6 rev. 1.6 05/15/07 figure 3 - simplified demo board schematic(mlpq) comp 32k 10k 100uf 1uh +1.05v 10a vout nx2141 pgnd ldrv hdrv sw fb bst pvcc 1uf 1uf 25tqc33m 25v,33uf vin1 +8 to 20v mbr0530t1 m1 m2 1uh co 2*2r5tpe220mc (220uf,12mohm) 0.1uf 1.5k 2.2nf 2.3k 15nf 1nf vin vin2 +5v 16 1 2 15 3 11 12 13 8 en 9 pgood 5 10k vcc 14 1uf 10 10 0.1uf gnd 17
nx2141 7 rev. 1.6 05/15/07 figure 4 - demo board schematic based on orcad
nx2141 8 rev. 1.6 05/15/07 bill of materials item number quantity reference part manufacturer 1 4 c1,c5,c6,c18 0.1u 2 4 c2,c4,c7,c9 1u 3 1 c3 25tqc33m sanyo 4 2 c19,c8 47u 5 1 c10 15nf 6 1 c13 1000pf 7 1 c14 2.2n 8 1 c15 470p 9 2 c17,c16 2r5tpe220mc sanyo 10 1 d1 mbr0530t1 11 1 l2 mlc1550-102ml coilcraft 12 1 m1 fds6294 fairchildsemi 13 1 m2 fds6676as fairchildsemi 14 4 r1,r2,r3,r11 0 15 3 r4,r6,r14 10 16 1 r5 100k 17 1 r8 2.3k 18 1 r10 32k 19 1 r12 10k 20 1 r13 1.5k 21 1 r15 1k 22 1 u1 NX2141CMTR nexsem inc. 23 1 u2 l78l05ab/sot89
nx2141 9 rev. 1.6 05/15/07 demoboard waveforms figure 8 - enlarged transient response(ch1 vout ac(50mv/div), ch2 output current(5a/div)) figure 7 - enlarged transient response(ch1 vout ac(50mv/div), ch2 output current(5a/div)) figure 5 - output ripple(ch1 vout ripple(50mv/ div),ch2 output current(5a/div), ch3 sw(5v/div)) figure 6 - transient response(ch1 vout ac(50mv/div), ch2 output current(5a/div)) figure 9 - over current protection(ch2 output current(10a/ div), ch4 vout(500mv/div)) figure 10 - power good(ch4 vout(500mv/div), ch3 pgood(5v/div))
nx2141 10 rev. 1.6 05/15/07 figure 11 - step vin response(ch1 vout ac(50mv/ div), ch3 vin(5v/div), ch4 sw(5v/div)) figure 12 - enlarged figure 11 (ch1 vout ac(50mv/ div), ch3 vin(5v/div), ch4 sw(5v/div)) figure 13 - step into precharged output (ch1 en (2v/ div), ch3 output current(10a/div), ch4 vout(500mv/div)) efficinecy vs iout(vin=19v) 74.00% 76.00% 78.00% 80.00% 82.00% 84.00% 86.00% 0 2 4 6 8 10 12 iout(a) efficiency(%) efficinecy vs iout(vin=12v) 79.00% 80.00% 81.00% 82.00% 83.00% 84.00% 85.00% 86.00% 87.00% 88.00% 89.00% 0 2 4 6 8 10 12 iout(a) efficiency(%) figure 14 - soft start(ch1 en(2v/div),ch2 output current(10a/div), ch3 vout(500mv/div)) demoboard waveforms(cont'd) figure 16 - efficiency(vin=19v, vout=1v) figure 15 - efficiency(vin=12v, vout=1v)
nx2141 11 rev. 1.6 05/15/07 application information symbol used in application information: v in - input voltage v out - output voltage i out - output current d v ripple - output voltage ripple f s - switching frequency d i ripple - inductor current ripple design example power stage design requirements: v inmin =8v v inmax =20v v out =1.05v i out_max =10a d v ripple <=30mv d v tran <=50mv @ 5a step f s =200khz output inductor selection the selection of inductor value is based on induc- tor ripple current, power rating, working frequency and efficiency. larger inductor value normally means smaller ripple current. however if the inductance is chosen too large, it brings slow response and lower efficiency. usu- ally the ripple current ranges from 20% to 40% of the output current. this is a design freedom which can be decided by design engineer according to various appli- cation requirements. the inductor value can be calcu- lated by using the following equations: inmaxout out out rippleinmaxs rippleoutput v-vv 1 l= ivf i=ki ...(1) where k is between 0.2 to 0.4. select k=0.4, then out out 20v-1.05v1.05v1 l= 0.410a20v200khz l=1.2uh in this application we choose l out =1uh, then coilcraft inductor mlc1550-102mlc is a good choice. current ripple @ maximum input voltage is calculated as inout out ripple outins v-vv 1 i= lvf 20v-1.05v1.05v1 =4.97a 1uh20v200khz = ...(2) output capacitor selection output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(dc) load condition as well as specification for the load transient. the optimum design may require a couple of iterations to satisfy both condition. based on dc load condition the amount of voltage ripple during the dc load condition is determined by equation(3). d d=d+ ripple rippleripple sout i vesri 8fc ...(3) where esr is the output capacitors' equivalent series resistance,c out is the value of output capacitors. typically when large value capacitors are selected such as aluminum electrolytic,poscap and oscon types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. for this example, poscap are chosen as output capacitors, the esr and inductor current typically de- termines the output voltage ripple. ripple desire ripple v 30mv esr=6m i4.97a d ==w d ...(4) if low esr is required, for most applications, mul- tiple capacitors in parallel are better than a big capaci- tor. for example, for 30mv output ripple, poscap 2r5tpe220mc with 12m w are chosen. eripple ripple esri n v d = d . ..(5) number of capacitor is calculated as 12m4.97a n 30mv w = n =2 the number of capacitor has to be round up to a integer. choose n =2.
nx2141 12 rev. 1.6 05/15/07 if ceramic capacitors are chosen as output ca- pacitors, both terms in equation (3) need to be evalu- ated to determine the overall ripple. usually when this type of capacitors are selected, the amount of capaci- tance per single unit is not sufficient to meet the tran- sient specification, which results in parallel configura- tion of multiple capacitors. for example, two 100uf, x5r ceramic capacitor with 2m w esr is used . the amount of output ripple is ripple 4.97a v1m4.97a 8200khz200uf 5mv15mv20mv d=w+ =+= two ceramic capacitors are needed. although this can meet dc ripple spec, however it needs to be stud- ied for transient requirement. based on transient requirement typically, the output voltage droop during transient is specified as d v droop d v tran < @step load d i step during the transient, the voltage droop during the transient is composed of two sections. one section is dependent on the esr of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. for example, for the over- shoot when load from high load to light load with a d i step transient load, if assuming the bandwidth of system is high enough, the overshoot can be esti- mated as the following equation. 2 out overshootstep out v vesri 2lc d=d+t ...(6) where t is the a function of capacitor,etc. crit step outcrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(7) where outouteeout crit stepstep esrcvesrcv l ii == dd ...(8) where esr e and c e represents esr and capaci- tance of each capacitor if multiple capacitors are used in parallel. the above equation shows that if the selected out- put inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the esr of output capacitor. for low frequency capacitor such as electrolytic capacitor, the product of esr and ca- pacitance is high and crit ll is true. in that case, the transient spec is mostly like to dependent on the esr of capacitor. most case, the output capacitor is multiple capaci- tor in parallel. the number of capacitor can be calcu- lated by the following estep 2 out tranetran esri v n v2lcv d =+t dd ...(9) where crit step eecrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(10) for example, assume voltage droop during tran- sient is 50mv for 5a load step. if the poscap 2r5tpe220mc(220uf, 12mohm esr) is used, the crticial inductance is given as eeout crit step esrcv l i 12m220f1.05v 0.55h 5a == d wm =m the selected inductor is 1uh which is bigger than critical inductance. in that case, the output voltage tran- sient not only dependent on the esr, but also capaci- tance. number of capacitor is step ee out li esrc v 1h5a 12m220f2.12us 1.05v d t=- m =-wm= estep 2 out tranetran 2 esri v n v2lcv 12m5a1.05v (2.12us) 53mv21h220f53mv 1.35 d =+t dd w =+ mm =
nx2141 13 rev. 1.6 05/15/07 the number of capacitors has to satisfy both ripple and transient requirement. overall, we choose n=2. it should be considered that the proposed equa- tion is based on ideal case, in reality, the droop or over- shoot is typically more than the calculation. the equa- tion gives a good start. for more margin, more capaci- tors have to be chosen after the test. typically, for high frequency capacitor such as high quality poscap es- pecially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the esr of capacitors is so low that the pcb parasitic can affect the results tremendously. more capacitors have to be selected to compensate these parasitic parameters. compensator design due to the double pole generated by lc filter of the power stage, the power system has 180 o phase shift , and therefore, is unstable by itself. in order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. ideally, the bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50 o and the gain crossing 0db with - 20db/decade. power stage output capacitors usually decide the compensator type. if electrolytic capacitors are chosen as output capacitors, type ii compensator can be used to compensate the system, because the zero caused by output capacitor esr is lower than cross- over frequency. otherwise type iii compensator should be chosen. voltage feedforward compensation is used in nx2141 to compensate the output voltage variation caused by input voltage changing. the feedforward funtion is realized by using vin pin voltage to program the oscil- lator ramp voltage v osc =0.1v in , which provides nearly constant power stage gain under wide voltage input range. a. type iii compensator design for low esr output capacitors, typically such as sanyo oscap and poscap, the frequency of esr zero caused by output capacitors is higher than the cross- over frequency. in this case, it is necessary to compen- sate the system with type iii compensator. the follow- ing figures and equations show how to realize the type iii compensator by transconductance amplifier. = p = p+ = p = p + z1 42 z2 233 p1 33 p2 12 4 12 1 f ...(11) 2rc 1 f ...(12) 2(rr)c 1 f ...(13) 2rc 1 f ...(14) cc 2r cc where f z1 ,f z2 ,f p1 and f p2 are poles and zeros in the compensator. the transfer function of type iii compensator for transconductance amplifier is given by: e mf out minin1 v 1gz v1gzz/r - = ++ for the voltage amplifier, the transfer function of compensator is e f out in v z vz - = to achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: r4>>2/gm. and it would be desir- able if r1||r2||r3>>1/gm can be met at the same time. zin zf vout vref fb r2 r1 r3 r4 c3 c1 c2 ve gm figure 17 - type iii compensator using transconductance amplifier
nx2141 14 rev. 1.6 05/15/07 case 1: f lc nx2141 15 rev. 1.6 05/15/07 case 2: f lc nx2141 16 rev. 1.6 05/15/07 b. type ii compensator design if the electrolytic capacitors are chosen as power stage output capacitors, usually the type ii compensa- tor can be used to compensate the system. for this type of compensator, f o has to satisfy f lc nx2141 17 rev. 1.6 05/15/07 1.set r 2 equal to10k w . using equation 18, the fi- nal selection of r 1 is 4.7k w. 2. set crossover frequency at 1/20 of the swithing frequency, here f o =10khz. 3.calculate r 3 value by the following equation. oscoout 3 inesrmref v2flv 1 r= vrgv 1210khz2.2uh1 = 1020.5m2.5ma/v 2.5v 0.8v =0.8k p p w w choose r 3 =1k w . 4. calculate c 1 by setting compensator zero f z at 75% of the lc double pole. 1 3z 1 c= 2rf 1 = 21k0.752.9khz =70nf p pw choose c 1 =68nf. 5. calculate c 2 by setting compensator pole p f at half the swithing frequency. 2 3s 1 c= rf 1 = 1k300khz =530pf p pw choose c 2 =560pf. output voltage calculation output voltage is set by reference voltage and ex- ternal voltage divider. the reference voltage is fixed at 0.8v. the divider consists of two ratioed resistors so that the output voltage applied at the fb pin is 0.8v when the output voltage is at the desired value. the following equation applies to figure 22, which shows the relation- ship between out v , ref v and voltage divider. . vout vref fb r2 r1 figure 22 - voltage divider 2ref 1 out ref rv r= v-v ...(18) where r 2 is part of the compensator, and the value of r 1 value can be set by voltage divider. input capacitor selection input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. ceramic ca- pacitors bypass the high frequency noise, and bulk ca- pacitors supply switching current to the mosfets. usu- ally 1uf ceramic capacitor is chosen to decouple the high frequency noise.the bulk input capacitors are de- cided by voltage rating and rms current rating. the rms current in the input capacitors can be calculated as: rmsout out inmin iid1-d v d v = = ...(19) v inmin = 8v, v out =1.05v, i out =10a, the result of input rms current is 3.4a. for higher efficiency, low esr capacitors are recommended. one sanyo oscon cap 25svp56m 25v 56uf 28m w with 3.8a rms rating are chosen as input bulk capacitors.
nx2141 18 rev. 1.6 05/15/07 where i out is output current, t sw is the sum of t r and t f which can be found in mosfet datasheet, and f s is switching frequency. swithing loss p sw is frequency dependent. also mosfet gate driver loss should be consid- ered when choosing the proper power mosfet. mosfet gate driver loss is the loss generated by dis- charg i ng the gate capacitor and is dissipated in driver circuits.it is proportional to frequency and is defined as: gatehgatehgslgatelgss p(qvqv)f =+ ...(22) where q hgate is the high side mosfets gate charge,q lgate is the low side mosfets gate charge,v hgs is the high side gate source voltage, and v lgs is the low side gate source voltage. this power dissipation should not exceed maxi- mum power dissipation of the driver device. over current limit protection over current limit for step down converter is achieved by sensing current through the low side mosfet. for nx2141, the current limit is decided by the r dson of the low side mosfet. when synchronous fet is on, and the voltage on sw pin is below 320mv, the over current occurs. the over current limit can be calculated by the following equation. setdson i320mv/r = the mosfet r dson is calculated in the worst case situation, then the current limit for mosfet irf7822 is set dson 320mv320mv i35a r1.46.5m === w layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. there are two sets of components considered in the layout which are power components and small sig- nal components. power components usually consist of input capacitors, high-side mosfet, low-side mosfet, inductor and output capacitors. a noisy environment is generated by the power components due to the switch- ing power. small signal components are connected to sensitive pins or nodes. a multilayer layout which in- cludes power plane, ground plane and signal plane is recommended . layout guidelines: 1. first put all the power components in the top layer connected by wide, copper filled areas. the input capacitor, inductor, output capacitor and the mosfets should be close to each other as possible. this helps to reduce the emi radiated by the power loop due to the high switching currents through them. 2. low esr capacitor which can handle input rms ripple current and a high frequency decoupling ceramic cap which usually is 1uf need to be practically touch- power mosfets selection the nx2141 requires two n-channel power mosfets. the selection of mosfets is based on maximum drain source voltage, gate source voltage, maximum current rating, mosfet on resistance and power dissipation. the main consideration is the power loss contribution of mosfets to the overall converter efficiency. for example, two irf7822 are used in appli- cation. they have the following parameters: v ds =30v, i d =18a,r dson =6.5m w ,q gate =44nc. there are two factors causing the mosfet power loss:conduction loss, switching loss. conduction loss is simply defined as: - + 2 hconoutds(on) 2 lconoutds(on) totalhconlcon p=idrk p=i(1d)rk p=pp ...(20) where the r ds(on) will increases as mosfet junc- tion temperature increases, k is r ds(on) temperature dependency. as a result, r ds(on) should be selected for the worst case, in which k approximately equals to 1.4 at 125 o c according to datasheet. conduction loss should not exceed package rating or overall system thermal budget. switching loss is mainly caused by crossover conduction at the switching transition. the total switching loss can be approximated. swinoutsws 1 pvitf 2 = . ..(21)
nx2141 19 rev. 1.6 05/15/07 4. drain of the low-side mosfet and source of the high-side mosfet need to be connected thru a plane ans as close as possible. a snubber nedds to be placed as close to this junction as possible. 5. source of the lower mosfet needs to be con- nected to the gnd plane with multiple vias. one is not enough. this is very important. the same applies to the output capacitors and input capacitors. 6. hdrv and ldrv pins should be as close to mosfet gate as possible. the gate traces should be wide and short. a place for gate drv resistors is needed to fine tune noise if needed. 7. vcc capacitor, bst capacitor or any other by- passing capacitor needs to be placed first around the ic and as close as possible. the capacitor on comp to gnd or comp back to fb needs to be place as close to the pin as well as resistor divider. 8. the output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. all gnds need to go directly thru via to gnd plane. 10. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. 11. in multilayer pcb, separate power ground and analog ground. these two grounds must be connected together on the pc board layout at a single point. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive ana- log control function. ing the drain pin of the upper mosfet, a plane connec- tion is a must. 3. the output capacitors should be placed as close as to the load as possible and plane connection is re- quired.
nx2141 20 rev. 1.6 05/15/07 mlpq 16 pin 3 x 3 package outline dimensions note: all dimensions are displayed in millimeters.
nx2141 21 rev. 1.6 05/15/07 mlpq 16 pin 3 x 3 tape and reel information note: 1. r7 = 7 inch lock reel, r13 = 13 inch lock reel. 2. all dimensions are displayed in millimeters.

▲Up To Search▲

Price & Availability of NX2141CMTR

	To Download NX2141CMTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .